On Shift Register Realization of Sequential Circuits

Realizing a sequential machine with shift registers is an attractive approach to the design for testability. It requires little extra circuit for scan and since feed-backs are always to the rst ip-op of a shift register test generation is expected to be easier than that for circuits with unstructured feedbacks. Though the shift register realization of sequential machines was studied by several researchers in 60's, there is still no satisfactory way of telling whether or not a given sequential machine is realizable with a given number of shift registers and/or ip-ops. This research is an attempt to nd a reasonable, if not optimum, way of realizing a sequential machine with shift registers. What is reported in this paper is a simple necessary and suucient condition for a given sequential circuit to be realizable with shift registers, an eecient algorithm to test whether or not a given sequential machine is realizable with shift registers, and a simple algorithm to nd a coding of the states is also given.